module control_plus (
  clk, reset, in, clr, count, show
);

  input clk, reset, in;
  // clr : 清空
  // show : 将显示在屏幕的计时器，1为甲，0为乙
  output reg clr, show;
  // count : 计时使能，count[1]为甲，count[0]为乙
  //         00时不计时，01时乙计时，11时都计时
  output reg [1:0] count;

  parameter S0 = 3'b000;
  parameter S1 = 3'b001;
  parameter S2 = 3'b010;
  parameter S3 = 3'b011;
  parameter S4 = 3'b100;

  reg[2:0] cur_state, nxt_state;

  always @(posedge clk) begin
    if ( reset ) cur_state <= S0;
    else         cur_state <= nxt_state;
  end

  always @(posedge clk) begin
    if ( reset ) nxt_state = S0;
    else begin
      case (cur_state)
        S0  : 
          if ( in ) nxt_state = S1;
        S1  :
          if ( in ) nxt_state = S2;
        S2  :
          if ( in ) nxt_state = S3;
        S3  :
          if ( in ) nxt_state = S4;
        S4  :
          if ( in ) nxt_state = S0;
      endcase
    end
  end

  always @(*) begin
    case (cur_state)
      S0  : begin
        clr   = 1;
        count = 2'b00;
        show  = 1;
      end
      S1  : begin
        clr   = 0;
        count = 2'b11;
      end 
      S2  : begin
        count = 2'b01;
        show  = 0;
      end
      S3  : begin
        count = 2'b0;
      end
      S4  : begin
        show  = 1;
      end
    endcase
  end

endmodule